The present invention relates to Dynamic Random Access Memory (DRAM), and more specifically to DRAM refresh schemes.
In Dynamic Data Rate (DDR) memory systems, a memory controller queues auto-refreshes to the memory device. During normal operation mode, the controller schedules refreshes in bursts to maximize performance. The DRAM maintains an internal refresh counter that tracks bank rows that get refreshed. When each auto-refresh command is received, the DRAM will either increment or decrement the refresh counter.
In an auto-refresh scheme, the memory controller does not know the exact addresses of the memory locations that are being refreshed. Thus, it is difficult to implement a sophisticated refresh management scheme to optimize power vs. performance.
With increased DRAM densities, the number of total pages to be refreshed increases substantially and, as a result, the overall refresh operation consumes an increasing amount of power. Because the controller must refresh all memory locations, whether or not the location is used for data, much power is wasted on unnecessary refresh cycles.
Partial array self refresh (PASR) DRAM is capable of refreshing ¼, ½, or ¾ of a bank of memory. This allows for some reduction in refresh power by reducing the number of memory locations to be refreshed during each refresh cycle. However, PASR DRAM does not allow a refresh start or end location to be specified.
As DRAM densities continue to increase, additional power can be saved by implementing more sophisticated refresh schemes